Abstract
Processor-in-memory (PIM) architectures have recently been proposed, with the objective of reducing the performance gap between processor and memory. An earlier study of Huang and Chu [Proceedings of 2nd Workshop on Intelligent Memory Systems, Cambridge, MA, 2000] designed a statement-based parallelizing system, SAGE, to exploit the potential benefits of PIM. This study extends this system to achieve better performance. Several comprehensive optimization approaches, including self-patch weight evaluation, loop splitting for PIM, intelligent memory operation (IMOP) recognition, and tiling for PIM, are devised to produce execution schedules with improved load balance. Experimental results confirm the effectiveness of the proposed method.
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