Improving the Performance of Aligned Carbon Nanotube-Based Transistors by Refreshing the Substrate Surface

Abstract

An aligned semiconducting carbon nanotube (A-CNT) array has been considered an excellent channel material to construct high-performance field-effect transistors (FETs) and integrated circuits (ICs). The purification and assembly processes to prepare a semiconducting A-CNT array require conjugated polymers, introducing stubborn residual polymers and stress at the interface between A-CNTs and substrate, which inevitably affects the fabrication and performance of the FETs. In this work, we develop a process to refresh the Si/SiO2 substrate surface underneath the A-CNT film by wet etching to clean the residual polymers and release the stress. Top-gated A-CNT FETs fabricated with this process show significant performance improvement especially in terms of saturation on-current, peak transconductance, hysteresis, and subthreshold swing. These improvements are attributed to the increase in carrier mobility from 1025 to 1374 cm2/Vs by 34% after the substrate surface refreshing process. Representative 200 nm gate-length A-CNT FETs exhibit an on-current of 1.42 mA/μm and a peak transconductance of 1.06 mS/μm at a drain-to-source bias of 1 V, subthreshold swing (SS) of 105 mV/dec, and negligible hysteresis and drain-induced barrier lowering (DIBL) of 5 mV/V.