Abstract
The die size of multistandard wireless transceivers in ultrascaled CMOS is dominated by the baseband low-pass filters (LPFs), which typically count on passive- $RC$ components to define the time constant. To break this area constraint, this paper revisits the active switched-capacitor (SC) LPF for its united benefits of clock-rate-defined bandwidth, accurate cutoff frequency, and small die size due to capacitor-ratio-based sizing and no spare elements. The key challenges of active-SC LPFs are the speed- and linearity-to-power tradeoffs, which are addressed by two circuit techniques: 1) switched-current assisting (SCA) and 2) precharging (PC). The SCA accelerates the charging speed of the integration capacitor, while the PC improves the linearity when charging the load capacitor. Three prototypes (first order, biquad, and fifth-order Butterworth) fabricated in a 65-nm CMOS process validate the feasibility of the proposed SCA and PC techniques.
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