Improving source/drain contact resistance of amorphous indium–gallium–zinc-oxide thin-film transistors using an n+-ZnO buffer layer

Abstract

To avoid high temperature annealing in improving the source/drain (S/D) resistance (RDS) of amorphous indium–gallium–zinc-oxide (α-IGZO) thin-film transistors (TFTs) for flexible electronics, a simple and efficient technique using a sputtering-deposited n+-ZnO buffer layer (BL) sandwiched between the S/D electrode and the α-IGZO channel is proposed and demonstrated. It shows that the RDS of α-IGZO TFTs with the proposed n+-ZnO BL is reduced to 8.1 × 103 Ω as compared with 6.1 × 104 Ω of the conventional one. The facilitation of carrier tunneling between the S/D electrode and the α-IGZO channel through the use of the n+-ZnO BL to lower the effective barrier height therein is responsible for the RDS reduction. Effects of the chamber pressure on the carrier concentration of the sputtering-deposited n+-ZnO BL and the thickness of the BL on the degree of improvement in the performance of α-IGZO TFTs are analyzed and discussed.