Improving Solder Joint Reliability for PoP Packages in Current Mobile Ecosystem

Abstract

Package on Package (PoP) has been an ideal choice for high end products in mobile ecosystem due to its high-density bandwidth support and flexibility for the original equipment manufacturers (OEMs) to accommodate required memory integration. Form-factor and performance requirements of high end handsets pushes the envelope of PoP package solutions in recent times and requires chip manufacturers to constantly shift package attributes. These changes often add various thermo-mechanical challenges for the chip manufacturers and end OEMs when integrating into their final system while maintaining high reliability requirement in field. In this paper, the focus will be primarily on addressing various attributes that concern the 2nd level solder interconnect reliability. We will discuss factors that affect both PoP memory BGAs and bottom logic package BGAs especially during temperature cycle (TC) condition. We will demonstrate a few case studies using both testing data and simulation data on how factors such as Memory BGA array, underfill choices and BGA depopulation can impact the board level reliability. We will further provide recommendations and guidelines to improve board level reliability of PoP packages in current ecosystem where OEMs are facing challenges juggling form-factor constraints, performance, functionality and field reliability.