Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors

Abstract

High-performance superscalar processors have been developed to satisfy the growing demand for processing modern applications. However, as the transistor size shrinks, the increase in vulnerability to soft errors poses a great challenge, since these effects have been proven to also affect ground-level safety-critical applications. Considering that vulnerability strategies may span across different layers of the system stack, we propose a mixed SW/HW-based design-time methodology aiming to achieve the best tradeoff between vulnerability and area/energy for superscalar processors. By injecting over 10 million faults in 12 significant micro-architectural structures to different versions of the complex BOOM OoO superscalar processor modeled with RTL accuracy, we show that SW-based protection techniques always reach an upper bound that may not be satisfactory. Then, we propose to insert extra low-level HW-based DMR protection at strategic micro-architectural points by reducing this task to the Knapsack Problem. In one of the evaluated cases, we optimally find the best structures to be protected with 55% area overhead to achieve a 95% vulnerability improvement for a quad-issue processor.