Improving Simulated Annealing-Based FPGA Placement With Directed Moves

Abstract

Simulated annealing remains a widely used heuristic for field-programmable gate array placement due, in part, to its ability to produce high-quality placements while accommodating complex objective functions. This paper discusses enhancements to annealing-based placement which improve upon both quality and run-time. Specifically, intelligent strategies for selecting and placing cells are interspersed with traditional random moves during an anneal, allowing the annealer to converge more quickly and to attain better quality with less statistical variability. For the same amount of computational effort, the contributions discussed in this paper consistently improve both critical path delay and wire length compared to traditional annealing perturbations.