Abstract
Waveform relaxation (WR) has been shown to be an effective algorithm to simulate large digital circuits. In this paper, we explore parallel WR methods to further improve the performance. The parallel processing issues under investigation include partitioning, task granularity, scheduling and allocation. The difficulty of addressing these issues is that circuit simulation problems tend to have highly irregular computational structures. The use of high-level waveforms generated from logic or timing simulators is introduced as a way of improving speed. The speed improvements for circuit partitioning, window selection and task allocation using high-level information are presented.
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