Improving linearity of CMOS power amplifier for LTE application

Abstract

A 2.6 GHz cascode CMOS power amplifier with the derivative superposition (DS) method and the second harmonic control for LTE application is fabricated in TSMC 1P6M 0.18 µm standard CMOS process. The DS method uses two transistors connected in parallel and biased in low and high inversions to compensate for the gm 3 and achieves the greater third-order intercept point (IIP3). The second harmonic control degrades the intermodulation distortion (IMD) and enhances the power added efficiency (PAE) performance. The simulation result shows that the circuit exhibited a power gain of 9.6 dB, an output power at P1dB of 19.5 dBm with a PAE of 39.5 % under 2.8 V voltage supply, an output third-order intercept point (OIP3) of 22 dBm and a power consumption of 26.54 mW.