Improving learning effectiveness with hands-on design labs and course projects for the operating model of a pipelined processor

Abstract

In teaching Computer Organization and Architecture courses, one of the major topics that reflect the techniques of high-performance processors is the analysis and design of high-performance pipelined processors. It covers three interrelated areas: computer architecture, computer organization and implementation. In the context of computer architecture, a pipelined processor works on the principle of exploiting instruction-level parallelism inside the pipeline and exploiting thread-level parallelism among multiple concurrently operating pipelines of a superscalar processor. During the study of computer organization and implementation, students often find it is difficult to understand (1) the operation of an instruction pipeline in its complicated space-time relationships of running an instruction stream over multiple stages of the pipeline, (2) the extensive existence of various types of data and control hazards among instructions, and (3) the distributed control mechanism of handling variable latencies of operations. To help students overcome these difficulties, we designed and developed a series of laboratory activities that were put together into a course project for the design and implementation of an operating model of a pipelined processor. Our multi-year experiences show that these activities and the course project significantly improved students' hands-on experience and understanding of the principle of operation of computer pipelines.