Abstract
This paper presents a link adaptation algorithm dedicated for 100Gbps wireless transmission. Interleaved Reed-Solomon codes are selected as forward error correction (FEC) algorithms. The redundancy of the codes is selected according to the channel bit error rate (BER). The uncomplicated FEC scheme allows implementing a complete data link layer processor in an FPGA (field programmable gate array). In our case, we use the Virtex7 FPGA to validate the functionality of our implementation. The proposed FPGA-processor achieves 169Gbps throughput. Moreover, the implementation is synthesized into 40nm CMOS technology and the described link adaptation algorithm allows reducing consumed energy per bit to values below 1pJ/bit at BER <1e−4. With higher BER, the energy increases up to ∼13pJ/bit.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: AEU - International Journal of Electronics and Communications
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
