Improving Digital Circuit Simulation with Batch-Parallel Logic Evaluation

Abstract

Integrated circuit simulators reproduce the behavior and functionality of the underlying circuits. They are part of FPGA CAD flow tools and they ensure the correctness of the circuits after the various conversions and optimizations occurring in the previous stages. During this procedure a graph with dependencies across nodes is created for each circuit design. Large circuits, and thus graphs, require more time to be simulated, making a parallel approach necessary. We explore a new solution-batch-parallel simulation in which the circuit output is calculated by worker threads that process batches of input vectors. The threads traverse and calculate their assigned nodes in parallel taking into consideration the intra-node dependencies. Furthermore, a node calculation analysis is performed and used to achieve work balance across threads. We apply this technique on the open-source Odin II framework and compare it with the existing approaches. The batch-parallel simulation is compared with the two existing approaches, single-threaded and multi-threaded, under various configurations, considering the number of threads and the batch sizes. The results demonstrate performance gains against the existing approaches in the majority of the benchmarks used for specific metrics, such as simulation elapsed time.