Improvement of the ON resistance of power VDMOS devices by surface doping: effect on the breakdown voltage

Abstract

An efficient way to improve the ON resistance R on of a vertical double-diffused MOS device is to implant a shallow, lightly doped layer over the drift area of the device. The evolution of R on for different voltage handling capacities vs. (i) the junction depth and (ii) the concentration of this layer was studied. The figure of merit (the product of R on and the surface area) of the device was calculated using an analytical unidimensional model and with a two-dimensional numerical simulator. The influence of this surface doping technique on the breakdown voltage of the device was investigated. Comparison between the analytical and numerical approaches shows that two-dimensional effects are important. The trade-off between the factor of merit and the breakdown voltage is emphasized and design rules to use the surface doping technique for devices with voltage handling capacities of 50, 150 and 400 V are given.