Improvement of productivity by spin coating nanoimprint lithography

Abstract

Nanoimprint lithography (NIL) has been received attention as an alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost, by transferring fine pattern of a template on to a resist layer by physical contact of template and resist followed by the resist curing. For more than a decade, we have been developing Jet and Flash Imprint Lithography (J-FIL) technology and challenging critical issues such as defect density, overlay, and throughput. J-FIL is an efficient process for transferring template pattern having large variations in pattern density. However, it has the intrinsic limitation of lower throughput due to resist dispensing time prior to imprinting of every single field on the wafer and the spreading process of resist drops, slow diffusion of bubble trapped at the resist drop-boundaries. To eliminate the above mentioned steps and improve throughput, we have developed a spin coating NIL (SCN) process in which a uniform resist layer is spin coated on the entire wafer. Identification of defect generation mechanism assuming Washburn’s model of capillary flow, has led us to optimize SCN process and thus achieving a higher throughput with lower defect density as compared to that of the J-FIL process. We will show the defect density and throughput performance of SCN process, and the possibility of introducing SCN in device production.