Abstract
We have been developing a Josephson-CMOS hybrid memory, with sub-nanosecond access time, in order to overcome a memory bottleneck in single-flux-quantum (SFQ) digital systems. In this paper, we describe two approaches to reduce the power consumption of 64-kb CMOS static RAMs. One is optimizing a decoder and memory cells based on high-sensitive Josephson current sensors, and the other is improving the data drivers. As a result, we decreased the power consumption of the decoder by 38% in the first approach, and decreased the power consumption of the total memory system by 80% in the Write 1 operation in the second approach. We aimed for demonstrating the full function of the 64-kb Josephson-CMOS hybrid memory with improved static RAMs. We have confirmed the correct operation in 6 channels for an 8b word address input in the 64-kb hybrid memory.
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