Improvement of Data Retention Time Property by Reducing Vacancy-Type Defect in DRAM Cell Transistor

Abstract

As electric equipment for portable spreads through a world widely, development of a low power consumption device is required strongly. DRAM development also has the same demand. Since DRAM needs a long refresh cycle in order to realize low power consumption, improvement of data retention time property is one of the important subjects. Among all the cell transistors in a DRAM chip, a few cells with short retention time, which are called minority bits, exist. Therefore, in order to get a long refresh cycle, it is indispensable to reduce the number of minority bits. The cause of minority bit generation has not been investigated in detail. In last year, however, we clarified one cause of the minority bit generation and proposed a new mechanism of data retention time degradation (Okonogi et al., 2004). Our results showed that the triangular intrinsic stacking faults in depletion layer of minority bits enhance junction leakage current through a trap-assisted tunneling. Since the defect is the aggregate of silicon vacancy at the compressive lattice strain region, the defect growth is suppressed by controlling the lattice strain. But, minority bit did not disappeared completely by this stress control. This result suggests that the small vacancy-type defect, such as point defect, still exists. In the present paper, the cause of the leakage current of a real DRAM cell was analyzed using EDMR (electrically detected magnetic resonance). The small point defect that remains in depletion region of a cell transistor was investigated. Furthermore, since one annealing process that enhances the occurrence of the point defect could be specified, the annealing condition dependence of the defect density was investigated. Consequently, for the first time, relationship between the number of minority bits and the density of point defect was clarified