Abstract
After the demonstration of feasibility of a new vertical thin film transistor (VTFT) based on low-temperature (T≤600°C) polycrystalline silicon (poly-Si) technology, some improvements were performed. The first fabrications gave evidence of some remaining drawbacks due to the relatively large area of common coverage between drain and source. As a result, relatively high offcurrent was observed that decreased the Ion/Ioff ratio. A way to significantly decrease the Ioff current consists in inserting a thin insulating layer between source and drain. Fabrication and electrical characterization of this new device confirmed the good approach that can be extended to other vertical architectures that are on progress.
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