Abstract
This paper presents the electrical characteristics of a short channel Silicon on Insulator (SOI) transistor with a graphene layer. The graphene sheet is used at the bottom of the channel close to the source side and a proportionally heavily p-type retrograde doping implanted in nearly middle of the channel. To increase the gate electrostatic control over the channel we incorporated a high-K material i.e. HfO2 as the gate oxide insulator. Due to Graphene growth and Retrograde Doping in the Channel, we called this structure “GRDC-SOI” transistor. Because graphene sheet has low band gap and high mobility, we used it to increase the on-state current. Engineered p-type retrograde doping utilized for both decreasing off-state current and increasing on-state current. These dopants cause impurity scattering in the depth of the channel and deflect electron movements and decrease off-current. On the other hand, these dopants which are located almost in the middle of the channel can play the role of base in an NPN Bipolar Junction Transistor (BJT), and turn it on and exceed the on-state current. An immense comparison among our proposed device and a device similar to GRDC-SOI but without Graphene sheet (RDC-SOI) and a conventional structure shows that our proposed device has superior electrical characteristics in terms of ION/IOFF ratio, transconductance, subthreshold slope, leakage current, breakdown voltage and short channel effects like hot carriers injection and DIBL. Our analyses demonstrate that GRDC-SOI transistor can open a window for utilizing Graphene material in digital circuits and system on chip applications.
Highlights
Since last decades, for expansion of Moore’s law and satisfying electronic industry requirements, shrinking of Metal Oxide Field Effect Transistors (MOSFET) have been continued [1]
Variety of transistors and materials used in RF circuits including bipolar transistors, n-channel MOSFETs and High Electron Mobility Transistors (HEMTs) [13,14].To open a bandgap in graphene and making it a semiconductor, several techniques are proposed including using bilayer graphene and applying a perpendicular field [15,16], narrowing graphene sheet in one dimension to form graphene nanoribbon [16,17], and applying strain to graphene
Graphene material is not defined in Silvaco Software, in order to have acceptable behavior in simulations, we utilized 3C-SiC material like the work carried out in the literature [23]
Summary
For expansion of Moore’s law and satisfying electronic industry requirements, shrinking of Metal Oxide Field Effect Transistors (MOSFET) have been continued [1]. For more electrostatic control over the channel and further increasing the on-current in the device, we used HfO2 material with dielectric constant of k = 16 [18,19,20,21], as gate insulator in the proposed device instead of SiO2 with k = 3.9 [22] in the C-SOI device. It should be noted that in this work the electrical characteristics of GRDC-SOI MOSFET is compared with RDC-SOI and C-SOI MOSFET counterparts where the active region including source, channel and drain regions are made from silicon material.
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