Improved uniformity in bonded SOI wafers with active layers from 1 to 30 μm at high throughputs

Abstract

We present here results of experiments in which we measured and processed bonded SOI wafers with active layers between 1 and 30 /spl mu/m at high throughput using the AcuThin/sup TM/ plasma-assisted chemical etch (PACE) process on our PWS-200 PACE system. The subject wafers were conventionally bonded, ground, and polished. We performed a single PACE process step on the wafers, removing approximately 2 /spl mu/m of silicon while improving the wafer uniformity. For one wafer, the global TTV (GBIR) of the active layer was improved from a starting value of 1.15 /spl mu/m to a final value of 0.14 /spl mu/m and the RMS uniformity of the surface improved from 0.238 to 0.023 /spl mu/m in the single process step. The experiment included off-line wafer measurement using two different metrology systems. For SOI layers less than 7 /spl mu/m, we used an IPEC Precision AcuMap II/sup TM/ to measure the wafers. For SOI layers between 7 and 30 /spl mu/m, we used an IPEC Precision IPM/sup TM/ thickness probe to measure the wafers. Assuming an average removal of 1.5 /spl mu/m on a 150 mm SOI wafer, the throughput of the PWS-200 would be 15 wafers per hour. The PWS-200 PACE system is a promising high-throughput method for producing SOI wafers for bipolar/BiCMOS applications.