IMPROVED TEST STIMULUS SCAN-IN METHOD FOR INTEGRATED CIRCUITS

Abstract

ABSTRACT: Scan testing is the key technology in the design for test of integrated circuit. For existing scan testing methods, the scan-in for test stimuli requires many clock cycles, which is one of the main restrictions of scan testing. To shorten the scan testing time of an integrated circuit, a novel test stimulus scan-in method was proposed in this study. First, scan chains, test stimuli, and test responses were grouped according to a fixed data width. Second, logic XOR calculation results of test response and test stimuli were coded according to the bit width of each group. The corresponding decoding and control circuits were added in the netlist of the circuit, which achieved fast input of test stimuli. Finally, an experiment using ISCA89 and IWLS2005 benchmark test circuits was performed. Experimental results were compared with those that used a serial input method of test stimuli. Results demonstrate that the proposed method can save approximately 37.5% and 43.7% of test time in average when the width of each group are 4 bits and 8 bits, respectively. The proposed method can decrease the clock cycles of scan testing significantly and shorten the scan testing time of the integrated circuit. Conclusions obtained in this study provide significant references for improving the scan testing method of digital integrated circuit. Keywords: Scan testing, Design for test, Test response, Test stimulus