Abstract
Due to paradigm shift from system-on-board to designs embracing embedded cores-based system-on-chips (SOCs), the complexity of digital circuits has enormously increased in recent times. This growing complexity has created a huge challenge in developing their appropriate and efficient fault testing environment. Despite enormous efforts directed towards effective testing of very large scale integrated (VLSI) circuit chips with reasonable cost, new frontiers emerged with advances in technology. The subject paper plans to develop a method to test verify circuit architecture under a hardware software co-design environment, specifically targeting embedded cores-based system-on-chips (SOCs). The concept of design-for-testability (DFT) is utilized in the paper together with ModelSim simulation and verification tool to test simulate the entire design. Some simulation results on ISCAS 85 combinational benchmark circuits are also included with a comparison of the results with some earlier works.
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