Abstract
The impact of a reduced package stray inductance on the switching performance of fast power MOSFETs is discussed applying advanced 3D packaging technologies. Starting from an overview over new packaging approaches, a solder bump technology using a flexible PI substrate is exemplarily chosen for the evaluation. Measurement techniques to determine the stray inductance are discussed and compared with a numerical solution based on the PEEC method. Experimental results show the improvement of the voltage utilization while there is only a slight impact on total switching losses.
Highlights
Fast power MOSFETs in the voltage class up to 100 V realize very high current and power densities while at the same time switching transients achieve times below 50 nanoseconds
Starting from an overview over new packaging approaches, a solder bump technology using a flexible PI substrate is exemplarily chosen for the evaluation
Measurement techniques to determine the stray inductance are discussed and compared with a numerical solution based on the PEEC method
Summary
Fast power MOSFETs in the voltage class up to 100 V realize very high current and power densities while at the same time switching transients achieve times below 50 nanoseconds. Apart from the LTJT, most of the proposed packaging solutions concentrate on a substitution of the wire bonds including alternatives like ribbon bonding [12] or spring contacts as well as planar interconnect technologies in 3dimensional stacked assemblies The latter include solutions with a prestructured circuit board, for example, a copper frame, a flexible substrate, or a second DBC that is usually soldered to the top side of the dice by solder bumping. There are several advantages anticipated from 3D sandwich assemblies including higher power density due to a compact layout, reduced interconnect resistances, and higher current rating compared to wire bonds as well as less parasitic stray inductance giving improved switching behavior and reduced overvoltage. DBC (c) Die bond on the DBC with flex deformation (thin Cu metallization) or die bond with preformed flex Figure 1: Process flow of the flip chip technology. (Right figures: photographs showing the prototype during the assembly process: (a) bumped MOSFET, (b) chips soldered to the flex, (c) complete assembly)
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of Power Management Electronics
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
