Improved short-channel FET performance with virtual extensions

Abstract

Here, for the first time, a method is presented to use electrostatic coupling from a metal of appropriate workfunction, separated from the extension region by a thin insulator, to create an electrostatically-induced charge layer in doped source/drain CMOS. This "virtual extension" allows for lower extension doping and increased underlap between the doped extension and the gate, "sharpening" the carrier profile and improving short-channel device performance. In one example, clock-limiting n-FET switching currents are improved 25% using this approach. However, the improvement in switching speed due to this higher current is partially offset by capacitance between the metal overlap and the extension.