Abstract
Improved result of TSV and Slew aware 3D Gated Clock Tree Synthesis using charge recycling configuration
Highlights
Nowadays, 3D physical design is a predominant solution in high performance computing systems
It is applied with Traditional 3D Clock Tree Synthesis (CTS) method
Maximum efforts are taken in eliminating the negative effect on clock skew along with slew rate and power
Summary
3D physical design is a predominant solution in high performance computing systems. Designers have the ability to accomplish a significant number of benefits towards utilizing TSVs, for example, shorter wire length, minimum wire delay, less power and smaller chip area. For short interconnected length and smaller package size TSV is most important in 3D ICs. To design a high-performance clock tree, the buffer size and selection of buffer are the most dominant factors because clock distribution network determines the clock skew. Clock skew arises from the interconnected delays due to load mismatch. In order to reduce the skew due to interconnect delays, selection of buffer size is an effective way. In order to optimize the power, clock gating logic is an important consideration in the performance of digital system. Uncertainties in the clock timing lead to the failure of the system
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