Abstract
The negative-bias-temperature-instability (NBTI) characteristic of PMOS high-k metal-gate (HKMG) bulk FinFETs with different interlayer (IL) fabrication process is investigated in this paper. Compared with chemical oxide IL, both post IL anneal and thermal oxidized IL can improve the device NBTI performance, which is due to the reduction of interface trap states during thermal process. Moreover, post IL anneal is found to be more effective in improving NBTI. The impact of IL process on device static electrical performance is also studied, which is detailed in the following.
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