Abstract

Further improvement of storage density is a key challenge for the application of phase-change memory (PCM) in storage-class memory. However, for PCM, storage density improvements include feature size scaling down and multi-level cell (MLC) operation, potentially causing thermal crosstalk issues and phase separation issues, respectively. To address these challenges, we propose a high-aspect-ratio (25:1) lateral nanowire (NW) PCM device with conventional chalcogenide Ge2Sb2Te5 (GST-225) to realize stable MLC operations, i.e., low intra- and inter-cell variability and low resistance drift (coefficient = 0.009). The improved MLC performance is attributed to the high aspect ratio, which enables precise control of the amorphous region because of sidewall confinement, as confirmed by transmission electron microscopy analysis. In summary, the NW devices provide guidance for the design of future high-aspect-ratio three-dimensional PCM devices with MLC capability.

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