Improved Modified Area Efficient Carry Select Adder (MAE-CSLA) Without Multiplexer

Abstract

The Carry Select Adder (CSLA) is the fastest adders that perform arithmetic operations in many processors. There are lot of modifications that are proposed to reduce the area of CSLA one such efficient technique is presented in this paper. Here the area is reduced by eliminating the multiplexer that selects the carry in of regular CSLA by using a simple XOR gate. Here the XOR gate is used to generate the first sum output of the ripple carry adders in the second stage of the CSLA adder. Then the XOR gate is implemented with AOI. This AOI implementation will further reduce the area consumption of the adder. The proposed Modified Area Efficient Carry Select Adder (MAE-CSLA) is designed and analyzed in XILINX ISE design suite 14.5 tools. By this analysis it is clear that the modifications effect adversely in the area and power consumption of MAE-CSLA.