Improved Memory Characteristics of A Novel TaN/Al2O3/TiO2/HfO2/SiO2/Si Structured Charge Trapping Memory

Abstract

In this work, we evaluate the program/erase/retention performance of a novel TaN/Al2O3/TiO2/HfO2/SiO2/Si (TATHOS) charge trapping memory (CTM) device with the stacked HfO2/SiO2 tunneling layer and TiO2 charge trapping layer by our developed simulator, which has included the critical mechanisms in CTM and has been verified with the experiment data. With various gate dielectric layer's thicknesses and materials, bias voltages and temperatures, the novel structure device's performance are studied and compared to some conventional devices. It can been seen that with appropriate design for the stack tunneling layer and TiO2 choice for the charge trapping layer, significantly improved program/erase speed and retention characteristics could be achieved. It can be a useful tool to optimize the performance of CTM with the gate layer materials' choice and design.