Improved linearity CMOS active resistor based on complementary computational circuits

Abstract

A new active resistor circuit will be presented in this paper. The main advantages of the original proposed implementation are the improved linearity, the small area consumption and the improved frequency response. An original technique for linearizing the I (V) characteristic of the active resistor will be proposed, based on the “mirroring” of the Ohm law from the input pins to another reference pins. The area consumption of the active resistor will be minimized by replacing the classical MOS transistor by a FGMOS (Floating Gate MOS) device. The circuit frequency response is very good as a result of biasing all MOS transistors in the saturation region and of a current-mode operation of the square-root circuit. The circuit is implemented in 0.35µm CMOS technology on a die area of 25µm × 35µm, being supplied at ± 6V . The circuit presents a very good linearity (THD < 0.6%) for an extended range of the input voltage ( − 5V <V X − V Y < 5V ). The tuning range is extremely large comparing with the previous reported active resistors: ± (600kΩ − 6MΩ) , the circuit being able to simulate both positive and negative active resistances.