Improved fabrication of fully-recessed normally-off SiN/SiO2/GaN MISFET based on the self-terminated gate recess etching technique

Abstract

The thermal-oxidation/wet-etching gate-recess mask using low-pressure-chemical-vapor-deposition (LPCVD) SiN/atomic-layer-deposition (ALD) AlN combined with high-quality LPCVD-SiN/ALD-SiO2 gate dielectric has been developed for the fabrication of normally-off GaN MISFETs by the self-terminated gate recess etching technique. The experimental results showed that the SiN/AlN layer could effectively hinder the formation of surface oxide on GaN cap, and ALD grown SiO2 could effectively protect the GaN channel from high-temperature damages by the following LPCVD. As a result, the fabricated devices exhibit a small on-resistance degradation, 200 mV hysteresis @ Vth = 2.4 V, <1 nA/mm gate leakage current and 6 × 108 on/off ratio.