Improved Crossbar Array Architecture for Compensating Interconnection Resistance: Ferroelectric HZO-Based Synapse Case

Mingfeng Tang,Xuepeng Zhan,Jiezhi Chen

doi:10.1109/jeds.2022.3150922

Mingfeng Tang, Xuepeng Zhan + Show 1 more

Open Access

https://doi.org/10.1109/jeds.2022.3150922

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Abstract

In-memory computing is a promising solution to break through the conventional von Neumann bottleneck. Owing to the low-power consumption, Si fabrication compatibility and fast switching speed, the HfZrOx (HZO)-based ferroelectric devices attract attention as artificial synapses. By using crossbar architectures, artificial synapse array can greatly speed up the efficiency for neuromorphic applications. However, interconnect resistance effect will cause a serious decrease in calculation accuracy. This paper proposes a crossbar array architecture with the HZO-based ferroelectric synapses, which can restore the current distortion caused by the interconnect resistance. At the device level, the synaptic potentiation and depression behaviors are achieved by adjusting the pulse duration. For the circuit level, the interconnect resistance can be significantly compensated. In neuromorphic computing, a high accuracy rate of 96% is realized, which can be further improved with the expansion of the array size. Our results provide a step towards the development of large-scale ferroelectric HZO-based neuromorphic devices.

Highlights

In-memory computing, showing fast calculation speed, is regarded as a promising candidate to break through the von Neumann bottleneck [1,2]
The ferroelectric synapse is composed of a 30nm TiN as the bottom electrode (BE), a 10nm HZO ferroelectric layer and a 40nm TiN as the top electrode (TE) and the electrode size is 100 m*100 m
A high-efficiency architecture is proposed in ferroelectric synapse crossbar arrays

Summary

INTRODUCTION

In-memory computing, showing fast calculation speed, is regarded as a promising candidate to break through the von Neumann bottleneck [1,2]. Wouters et al proposed a PCM-based resistive switching memories, but its application is limited by the high energy consumption [10]. Yan Liao et al [16] and Lin Bao et al [22] replaced Kirchhoff's equations with a new algorithm to improve computational efficiency. It still requires data transmission on the data bus, which reduces the advantages of the in-memory computing. A new resistance crossbar array architecture based on the HZO ferroelectric device is proposed. The duration of the voltage pulse, the multi-level residual polarization states are obtained in ferroelectric synapse.

FERROELECTRIC SYNAPSE

IMPROVED CIRCUITS METHOD

APPLICATION IN DNN CALCULATION

Findings

CONCLUSION