Abstract
The sample-and-hold (S/H) circuit is an important part of the ADC. An improved complementary bootstrap switch is proposed in this paper. A negative voltage bootstrap capacitance is introduced to reduce the parasitic capacitance of key nodes by minimizing the size of the transistor. The sampling MOSFET in this structure is composed of complementary NMOS and PMOS, which reduces the channel charge injection effect. The simulation results show that the effective number of bits (ENOB), signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the structure are 16.5 bits, 101.11 dB and 101.83 dB respectively at the sampling frequency of 50 MHz and full swing voltage input of 1.8V based on SMIC 0.18 μm process. Compared with the traditional NMOS switch, ENOB, SDNR, and SFDR are increased by 2.3 bits, 14.9 dB, and 13.3 dB, respectively.
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