Improved and Reduced-Order I/O Devices Behavioral Modeling Solutions for SI Simulation

Abstract

This chapter presents the parametric and equivalent circuit solutions for improving the I/O buffer behavioral modelling. The previously neglected driver’s nonlinear dynamic effects are efficiently captured to significantly reduce the state of the art black-box parametric modeling complexities and enhance the input/output buffers information specifications (IBIS). This is achieved by following the gray-box approach that merges the features of the black-box model’s formulation and the analysis of the observed I/O electrical signals and the analysis of the buffer’s physical structure properties under practical operation conditions. This approach leads to physically inspired behavioral model’s construction procedure that overcomes the issues of the previous modeling approaches by optimizing the resources used at different model’s generation steps (i.e. characterization, formulation, extraction, and implementation) to mimic the driver’s nonlinear dynamic behavior. In the conceived parametric solution, the output current relationship with the output voltage is expressed as a summation of a static nonlinearity plus linear dynamics. This separation in the model format is supported by both measurements and the physical structure of a general driver circuit. This approach merges the features of equivalent circuit and the parametric approaches to build a reduced-order parametric behavioral model which, compared to other published models, is more adequate to describe the device’s electrical behavior from transient input-output data. Furthermore, an efficient and accurate table-based behavioral model extraction for high speed input/output buffer behavior is presented in this work. The nonlinear voltage-current (I-V) and voltage-charge (Q-V) functions describing the grey-box model structure are extracted via the bias-dependent S-parameters frequency domain measurements or the least squares methods using identification signals recorded from large signal transient simulation. Finally, the development of a new two-port analog behavioral model for overclocking simulation that copes with the recent trends in I/O memory interfaces characterized by higher data rate transmission. The effectiveness and the accuracy of the developed and implemented parametric and equivalent circuit behavioral models are qualitatively and quantitatively assessed by comparing the numerical results of their functions extraction and transient simulation to the ones simulated and extracted with transistor level models and the state of the art IBIS in order to validate their predictive and the generalization capabilities.