Improve overlay performance against process variation impact by using overlay metrology recipe optimization

Abstract

In high volume semiconductor production (HVM) environment, overlay (OVL) metrology is becoming more challenging due to the increasing process variation impact on the quality of the metrology target. Process variation from a variety of sources, including deposition, etching, CMP, etc. impacts OVL performance - lot by lot, wafer by wafer, or even within wafer. To improve the OVL performance and minimize the impact of process variation, both root cause analysis and metrology recipe optimization are critical. In this paper, we studied the impact of intra wafer CMP process variation on OVL metrology performance using 2x nm node logic layers. Often, the polishing process may cause wafer center to edge variation and large OVL vectors on the wafer edge region. One solution is to design and utilize a new target design which would be more robust to the process variability impact to the target. However, a new OVL target design requires time and cost to manufacture a new reticle. In this paper, we improve the OVL metrology tolerance to variability through metrology recipe optimization. Using the image-based overlay (IBO) metrology tool wavelength tunning function, we capture the key OVL indices across the tool's spectrum. Using variability input from the full wafer, the risk information of the full spectrum is then utilized to quantify and achieve better OVL performance. By selecting the best wavelength and polarization on the overlay metrology tool, the residual and on product OVL (OPO) results are improved with better accuracy.