Improve accuracy of delay element by filtering false path for low power desychronized circuits

Abstract

Desynchronized circuits outperform the synchronous counterparts in power, performance, robustness according to many studies, and delay elements are important components by mimicking the critical path delay of two arbitrary correlated latches to act as completion detection logic. In classical design flow, the critical path delay is derived through static timing analysis (STA); however, this approach may cause conservative results since STA can not identify false paths which are never activated in real life. In this paper, we firstly prove that existence of false path is a common phenomenon by making an experiment on ISCAS89 benchmarks, and then propose a fast and easy filtering method by utilizing ATPG technique. A case study on an industrial design block shows its effectiveness in improving performance, area and power.