Abstract
We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal verification of digital systems. Assertion graphs are used for property and model specifications. We present a novel implication technique for assertion graphs. It relies on direct Boolean reasoning on each edge (and vertex) of an assertion graph, thus avoiding the reachability computation in GSTE. We have successfully applied. both model-based and language-based implications on real industrial circuits. Experimental results demonstrate the promising performance of our approach.
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