Abstract
A method for the design of low-cost near-exact Discrete Cosine Transform (DCT) approximations on the Xilinx Virtex FPGA is presented. This method can be used to control the coding gain, Mean Square Error (MSE), quantization noise, hardware cost, and power consumption of the DCT approximation. The Xilinx Place-And-Route (PAR) process and XPWR are used to gauge the hardware cost and the power consumption respectively. It is shown that it is possible to generate FPGA based DCT approximations with near optimal coding gains that meet the Mean Square Error (MSE), hardware cost, quantization noise, and power consumption requirements.
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