Abstract

Implementing sparse estimation efficiently in digital hardware is crucial for real-time applications. For such an implementation one typically favours lightweight iterative algorithms. This not only keeps the complexity low, but also allows a fine-granular tuning of the performance/complexity trade-off. Recently, algorithms based on Linearized Bregman Iterations (LBI) have shown to be very feasible for low complexity digital hardware implementation. An alternative approach would be to use cyclic coordinate descent (CCD) algorithms. However, the state-of-the-art formulation of sparse cyclic coordinate descent has properties preventing an efficient hardware implementation. In this work, we propose variations of cyclic coordinate descent, specifically tailored for digital efficient hardware implementation. These modifications allow cyclic coordinate descent algorithms to be competitive in a hardware implementation compared to the implementation efficient Linearized Bregman iteration algorithms. We show simulation results for different sparse estimation use-cases demonstrating the capabilities of both methods. We also identify scenarios where our CCD approach allows to obtain the same performance with less complexity than LBI.

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