Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor

N Suzuki,T Awashima,N Kaneko,K Deguchi,T Toi,S Kurotaki,M Motomura,M Suzuki,Y Yamada,H Amano,K Anjo,Y Hasegawa,K Wakabayashi

doi:10.1109/fccm.2004.42

Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor

N Suzuki, T Awashima + Show 11 more

https://doi.org/10.1109/fccm.2004.42

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Publication Date: Jul 10, 2015

Citations: 14

Affiliation: Keio University, NEC (Japan)

#Dynamically Reconfigurable Processor #Reconfigurable Processor + Show 8 more

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Abstract

Dynamically reconfigurable processor (DRP) developed by NEC electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the first prototype chip, and evaluation results are presented. By computing parallelly using the processing elements(PEs) and distributed memory modules, DRP-1 outperformed pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance.

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