Implementation, Scheduling, and Adaptation of Partial Expansion Graphs on Multicore Platforms

Abstract

The dynamic nature of state-of-the-art multicore signal processing systems limits the ability of designers to derive accurate models for the targeted applications. Inaccurate assumptions in the model can lead to inefficient implementations and restrict the runtime re-configuration of these systems. On the other hand, dataflow models have provided powerful techniques to analyze and explore the design space for many classes of signal processing systems. In this context, we develop the Partial Expansion Graph (PEG) as an implementation model where existing dataflow graph analysis is augmented with dynamic adaptation, efficient parallelism utilization, and online reconfiguration based on the measured performance of the targeted applications. In this paper, we develop new methods for scheduling and mapping DSP systems using PEGs. Collectively, these methods tune the amount of data parallelism in the application graph and distribute data- and task-parallel instances over different cores while balancing the load across the available processing units. We enable online adaptation for PEG systems using low-overhead customizable solutions. We demonstrate the utility of our PEG-based scheduling and mapping algorithms through experiments on real application models and various synthetic graphs.