Implementation- performance analysis of high speed MAP decoder for long term evolution

Abstract

Due to high error correcting capability turbo coding is highly used in digital communication systems. In this article a new design of turbo decoder with reduced dynamic power dissipation is presented. In this modified decoder, standard cell based design using pipeline logarithm-maximum a posterior (Log-MAP) algorithm with clock gating and variable number of iteration is used to reduce the area and to increase the throughput. The information rate of 100 Mbps will be bolstered by forthcoming 3G Long Term Evolution (LTE) standards. In 20 MHZ of transfer speed, this information rate will be accomplished. For the entry of high information rate of the 3G LTE frameworks, there is a key prerequisite of turbo decoder execution. In this work, Log-MAP computation based turbo decoder for LTE beneficiary is proposed. The Log-MAP established turbo decoder gives execution closer as far as possible with sensible computational unpredictability. The VHDL coding for parallel design of turbo decoder utilizing Log-MAP calculation for LTE is recreated and combined utilizing Xilinx14.2, Spartan 3 family and the outcomes are checked with the manual count.