Implementation on <i>FPGA</i> of Neuro-Genetic PID Controllers Auto-Tuning

Abstract

The present paper studies the use of genetic algorithm to optimize the tuning of the Proportional, Integral and Derivative (PID) controller. Two control criteria were considered, the integral of the time multiplied by the absolute error (ITAE), and the integral of the time multiplied by the absolute output (ITAY). The time variant plant tested is a first-order plant with time delay. We aim at a real time implementation inside a digital board, so, the previous continuous approach was discretized and tested; the corresponding control algorithm is presented in this paper. The genetic algorithms and the PID controller are executed using the soft processor NIOS II in the Field Programmable Gate Array (FPGA). The computational results show the robustness and versatility of this technology.