Abstract
Due to the ever growing demand for high speed processors advancement in the technology regards to speed is the peak area of interest. The first word strikes when the parameter speed is concerned is multiplication. Since multiplication is an important fundamental function in all mathematical computations it dominates the execution time of most throughput determination & CPU cycle time of a system. In this paper, we develop a novel architecture to perform high speed multiplication using ancient vedic mathematics. One of the most efficient sutra in vedic mathematics named as Urdhva Triyakbhyam strikes a difference in the actual multiplication process. The Adder employed in implementing the paper is Kogge stone adder which is a parallel prefix form of carry look ahead adder & widely used adder in the industries of the present day. Since the adder used generates the carry signal in O(logn) time, it is widely considered to be the fastest adder design possile. The proposed algorithm is developed using verilog HDL. Implementation has been done using Xilinx14.6, Spartan6 FPGA.
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