Implementation of Systolic Co-processor for Deep Neural Network Inference based on SoC

Abstract

In this paper, we present an implementation of systolic co-processor for Deep Neural Network (DNN) inference. The co-processor is used in matrix multiplication between input on every DNN layer and weight values for corresponding DNN layer. The co-processor is implemented on FPGA inside the programmable System-on-Chip (SoC). The co-processor can be accessed from the ARM Cortex-A9 processor through the AXI4 bus. The DNN inference result from the co-processor has been verified by comparing to the MATLAB simulation. The coprocessor has been implemented on Xilinx Zynq-7000 SoC. The computation result has been verified by comparing to the MATLAB simulation.