Implementation of sphere decoder with early termination using FPGA

Abstract

Sphere Decoding (SD) algorithm has emerged as a highly effective detection scheme for Multiple-Input Multiple-output (MIMO) systems. It offers a near maximum likelihood accuracy with reduced complexity. Despite this, there is a constant demand of even low complexity SD algorithms. This paper presents the FPGA implementation of Schnorr-Euchner SD algorithm with Early Termination (ET) scheme for uncoded multiple-input multiple output system. The ET scheme reduces the complexity of the decoder. The proposed decoder is designed for 4×4 Binary Phase Shift Keying (BPSK) MIMO system. The trade-off between the Bit Error Rate (BER) performance and the computational complexity is discussed. To compute the computational complexity synthesis of the proposed design is done on Xilinx Virtex 5 XC5VLX30T and Spartan 6 XC6SLX25T. An exhaustive comparison on the basis of resources utilized and frequency (MHz) at which the design can run is done on both the FPGAs.