Implementation of Sparse Superposition Codes

Abstract

Sparse superposition codes (SSCs) are capacity achieving codes whose decoding process is a linear sensing problem. Decoding approaches thus exploit the approximate message passing algorithm, which has been proven to be effective in compressing sensing. Previous work from the authors has evaluated the error correction performance of SSCs under finite precision and finite code length. This paper proposes the first SSC encoder and decoder architectures in the literature. The architectures are parametrized and applicable to all SSCs: A set of wide-ranging case studies is then considered, and code-specific approximations, along with implementation results in 65 nm CMOS technology, are then provided. The encoding process can be carried out with low power consumption ( $\leq \text{2.103}$ mW), while the semi-parallel decoder architecture can reach a throughput of 1.3 Gb/s with a $768\times 6$ -bit SSC codeword and an area occupation of 2.43 mm $^2$.