Abstract
In present days, image processing is very much needed in different fields like medicine, acoustics, forensic sciences, agriculture, and industrial applications. These image processing algorithms are most preferably implemented on field-programmable gate arrays (FPGA) as they are reprogrammable to perform required operations. This paper describes the implementation of histogram equalization on Zynq FPGA which consists of ARM cortexA9 processor along with FPGAs. To implement this, Intellectual Property (IP) cores are generated in Vivado high-level synthesis (HLS) tool to figure out and equalize the histogram. These IP cores are brought down to Vivado to create the required hardware. Finally, the design was programmed into Zynq FPGA. The software application is developed using software development kit (SDK). The results are obtained for an image size of 259 × 194. The utilization report shows that implemented design has taken less number of hardware resources as compared with the Kintex KC705 evaluation board. The processing time taken for execution is 9.288 nsec.
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