Implementation of Reed Solomon Encoder on Low-Latency Embedded FPGA in Flexible SoC based on ARM Processor

Abstract

Having high efficiently embedded systems is important for various applications, especially, for modern communication systems, wireless sensor networks, mobile networks, and digital storage systems. Therefore, an efficient error control and correction solution in digital data is an important issue to ensure data protection. In this context, Reed Solomon codes are often used for error corrections. These embedded applications are implemented as software cores, hardware cores or a mixture of software-hardware Intellectual Property (IPs). In this paper authors proposes an efficient metric to improve performance, flexibility and cost of Reed Solomon (RS) Encoder by implementing this algorithm in Re-configurable System on Chip (SoC). The proposed system is composed of a low power ARM processor connected to a hierarchical embedded Field Programmable Gate Array (FPGA) to ensure the acceleration task with the best low-latency which targets a wide range of applications. This is the first reconfigurable SoC composed by Tree-based embedded FPGA that targets the RS-Encoder algorithm. The first contribution is the design of a complete SoC integrating a software embedded FPGA (eFPGA) which is fully synthesized and implemented into an FPGA platform. The second added value is that the embedded FPGA size can go up to 4 KLUTS with a big number of inputs/outputs. The third contribution is that the proposed SoC targets one of the most powerful algorithms. The eFPGA integration introduces a chip area overhead but it proves interesting results in terms of run-time. Indeed, for 100 software instructions, the eFPGA is faster 4 times compared to a hardware accelerator and 412 times compared to the software implementation of the RS algorithm.