Implementation of real-time Laplacian pyramid image fusion processing based on FPGA

Abstract

In this paper, a novel method is proposed to implement Laplacian pyramid image fusion on FPGA. Firstly, implementation of image fusion algorithm based on Programable DSP (PDSP) and FPGA is compared, as well as the advantages of Laplacian pyramid for parallel processing. Secondly, the architecture and characters of Laplacian pyramid is analyzed in detail. Finally the related logical modules in FPGA are designed according to their functions of this algorithm, including controlling module, decomposing module, fusion module and reconstruction module. Inside the decomposing module, 3-stage pipeline is designed for decomposing images at each level. Three-level Laplacian pyramid image fusion algorithm is adopted through Verilog Hardware Description Language according to the designed methods forementioned. The design is verified on a real-time dual-channel image fusion system based on Virtex-4 SX35 FPGA. The experiment results show that the fusion system can realize real-time image fusion processing for dual channels 640×480 images at the rate of 25 frames per second. Comparing with input digital video stream, the output video stream delays less than 10 horizontal line clocks.