Implementation of pipelined Booth Encoded Wallace tree Multiplier architecture

Abstract

The Booth multiplier is a very fast multiplier with minimum latencies. In this paper, a typical architecture of Booth Encoder and Wallace tree is presented, In which we have implemented pipelining at the intermediate nodes of the modules present in it. The architecture comprises of four modules, they are as follows, One's Complement generator, Booth Encoder, Partial product generator and Wallace tree adder accompanied by Ripple carry adder respectively. The Wallace tree adder and Booth multiplier are typically used for high speed computations. One such application is a DSP processor. In this paper we have designed a four stage pipelining at the intermediate nodes mentioned above. This will help in performing many arithmetic operations simultaneously and hence increase the speed as well as computation of simultaneous inputs. The design is implemented in Verilog HDL. The simulation is done on Cadence NC Sim while the synthesis is carried out in Cadence RTL Compiler using TSMC 45nm slow.lib.